1. Field of the Invention
The present invention relates to programmable memory devices, such as programmable resistive devices for use in memory arrays.
2. Description of the Related Art
A programmable resistive device is generally referred to a device's resistance states that may change after means of programming. Resistance states can also be determined by resistance values. For example, a resistive device can be a One-Time Programmable (OTP) device, such as electrical fuse, and the programming means can apply a high voltage to induce a high current to flow through the OTP element. When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state (depending on either fuse or anti-fuse).
An electrical fuse is a common OTP which is a programmable resistive device that can be constructed from a segment of interconnect, such as polysilicon, silicided polysilicon, silicide, metal, metal alloy, or some combination thereof. The metal can be aluminum, copper, or other transition metals. One of the most commonly used electrical fuses is a CMOS gate, fabricated in silicided polysilicon, used as interconnect. The electrical fuse can also be one or more contacts or vias instead of a segment of interconnect. A high current may blow the contact(s) or via(s) into a very high resistance state. The electrical fuse can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher. The anti-fuse can consist of one or more contacts or vias with an insulator in between. The anti-fuse can also be a CMOS gate coupled to a CMOS body with a thin gate oxide as insulator.
The programmable resistive device can be a reversible resistive device that can be programmed into a digital logic value “0” or “1” repetitively and reversibly. The programmable resistive device can be fabricated from phase change material, such as Germanium (Ge), Antimony (Sb), and Tellurium (Te) with composition Ge2Sb2Te5 (GST-225) or GeSbTe-like materials including compositions of Indium (In), Tin (Sn), or Selenium (Se). Another phase change material can include a chalcogenide material such as AgInSbTe. The phase change material can be programmed into a high resistance amorphous state or a low resistance crystalline state by applying a short and high voltage pulse or a long and low voltage pulse, respectively.
Another type of reversible resistive device is a class of memory called Resistive RAM (RRAM), which is a normally insulating dielectric, but can be made conducting through filament, defects, metal migration, etc. The dielectric can be binary transition metal oxides such as NiO or TiO2, perovskite materials such as Sr(Zr)TiO3 or PCMO, organic charge transfer complexes such as CuTCNQ, or organic donor-acceptor systems such as Al AlDCN. As an example, RRAM can have cells fabricated from metal oxides between electrodes, such as Pt/NiO/Pt, TiN/TiOx/HfO2/TiN, TiN/ZnO/Pt, or W/TiN/SiO2/Si, etc. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, voltage/current-limit, or the combinations thereof to generate or annihilate conductive filaments. Another programmable resistive device similar to RRAM is a Conductive Bridge RAM (CBRAM) that is based on electro-chemical deposition and removal of metal ions in a thin solid-state electrolyte film. The electrodes can be an oxidizable anode and an inert cathode and the electrolyte can be Ag- or Cu-doped chalcogenide glass such as GeSe, Cu2S, or GeS, etc. The resistance states can be changed reversibly and determined by polarity, magnitude, duration, voltage/current-limit, or combinations thereof to generate or annihilate conductive bridges. The programmable resistive device can also be an MRAM (Magnetic RAM) with cells fabricated from magnetic multi-layer stacks that construct a Magnetic Tunnel Junction (MTJ). In a Spin Transfer Torque MRAM (STT-MRAM) the direction of currents applied to an MTJ determines parallel or anti-parallel states, and hence low or high resistance states.
A conventional programmable resistive memory cell 10 is shown in FIG. 1. The cell 10 consists of a resistive element 11 and an NMOS program selector 12. The resistive element 11 is coupled to the drain of the NMOS 12 at one end, and to a high voltage V+ at the other end. The gate of the NMOS 12 is coupled to a select signal (Sel), and the source is coupled to a low voltage V−. When a high voltage is applied to V+ and a low voltage to V−, the resistive cell 10 can be programmed by raising the select signal (Sel) to turn on the NMOS 12. One of the most common resistive elements is a silicided polysilicon, the same material and fabricated at the same time as a MOS gate. The size of the NMOS 12, as program selector, needs to be large enough to deliver the required program current for a few microseconds. The program current for a silicided polysilicon is normally between a few milliamps for a fuse with width of 40 nm to about 20 mA for a fuse with width about 0.6 um. As a result, the cell size of an electrical fuse using silicided polysilicon tends to be very large. The resistive cell 10 can be organized as a two-dimensional array with all Sel's and V−'s in a row coupled as wordlines (WLs) and a ground line, respectively, and all V+'s in a column coupled as bitlines (BLs).
Another conventional programmable resistive device 20 for Phase Change Memory (PCM) is shown in FIG. 2(a). The PCM cell 20 has a phase change film 21 and a bipolar transistor 22 as program selector with P+ emitter 23, N base 27, and P sub collector 25. The phase change film 21 is coupled to the emitter 23 of the bipolar transistor 22 at one end, and to a high voltage V+ at the other. The N type base 27 of bipolar transistor 22 is coupled to a low voltage V−. The collector 25 is coupled to ground. By applying a proper voltage between V+ and V− for a proper duration of time, the phase change film 21 can be programmed into high or low resistance states, depending on voltage and duration. Conventionally, to program a phase-change memory to a high resistance state (or reset state) requires about 3V for 50 ns and consumes about 300 uA of current, or to program a phase-change memory to a low resistance state (or set state) requires about 2V for 300 ns and consumes about 100 uA of current.
FIG. 2(b) shows a cross section of a conventional bipolar transistor 22. The bipolar transistor 22 includes a P+ active region 23, a shallow N well 24, an N+ active region 27, a P type substrate 25, and a Shallow Trench Isolation (STI) 26 for device isolation. The P+ active region 23 and N+ active region 27 couple to the N well 24 are the P and N terminals of the emitter-base diode of the bipolar transistor 22, while the P type substrate 25 is the collector of the bipolar transistor 22. This cell configuration requires an N well 24 be shallower than the STI 26 to properly isolate cells from each other and needs 3-4 more masking steps over the standard CMOS logic processes which makes it more costly to fabricate.
Another programmable resistive device 20′ for Phase Change Memory (PCM) is shown in FIG. 2(c). The PCM cell 20′ has a phase change film 21′ and a diode 22′. The phase change film 21′ is coupled between an anode of the diode 22′ and a high voltage V+. A cathode of the diode 22′ is coupled to a low voltage V−. By applying a proper voltage between V+ and V− for a proper duration of time, the phase change film 21′ can be programmed into high or low resistance states, depending on voltage and duration. The programmable resistive cell 20′ can be organized as a two dimensional array with all V−'s in a row coupled as wordline bars (WLBs), and all V+'s in a column coupled as bitlines (BLs). As an example of use of a diode as program selector for each PCM cell as shown in FIG. 2(c), see Kwang-Jin Lee et al., “A 90 nm 1.8V 512 Mb Diode-Switch PRAM with 266 MB/s Read Throughput,” International Solid-State Circuit Conference, 2007, pp. 472-273. Though this technology can reduce the PCM cell size to only 6.8 F2 (F stands for feature size), the diode requires very complicated process steps, such as Selective Epitaxial Growth (SEG), to fabricate, which would be very costly for embedded PCM applications.
FIGS. 3(a) and 3(b) show several embodiments of an electrical fuse element 80 and 84, respectively, fabricated from an interconnect. The interconnect serves as a particular type of resistive element. The resistive element has three parts: anode, cathode, and body. The anode and cathode provide contacts for the resistive element to be connected to other parts of circuits so that a current can flow from the anode to cathode through the body. The body width determines the current density and hence the electro-migration threshold for a program current. FIG. 3(a) shows a conventional electrical fuse element 80 with an anode 81, a cathode 82, and a body 83. This embodiment has a large symmetrical anode and cathode. FIG. 3(b) shows another conventional electrical fuse element 84 with an anode 85, a cathode 86, and a body 87. This embodiment has an asymmetrical shape with a large anode and a small cathode to enhance the electro-migration effect based on polarity and reservoir effects. The polarity effect means that the electro-migration always starts from the cathode. The reservoir effect means that a smaller cathode makes electro-migration easier because the smaller area has lesser ions to replenish voids when the electro-migration occurs. The fuse elements 80, 84 in FIGS. 3(a) and 3(b) are relatively large structures which makes them unsuitable for some applications.
FIGS. 4(a) and 4(b) show programming a conventional MRAM cell 210 into parallel (or state 0) and anti-parallel (or state 1) by current directions. The MRAM cell 210 consists of a Magnetic Tunnel Junction (MTJ) 211 and an NMOS program selector 218. The MTJ 211 has multiple layers of ferromagnetic or anti-ferromagnetic stacks with metal oxide, such as Al2O3 or MgO, as an insulator in between. The MTJ 211 includes a free layer stack 212 on top and a fixed layer stack 213 underneath. By applying a proper current to the MTJ 211 with the program selector CMOS 218 turned on, the free layer stack 212 can be aligned into parallel or anti-parallel to the fixed layer stack 213 depending on the current flowing into or out of the fixed layer stack 213, respectively. Thus, the magnetic states can be programmed and the resultant states can be determined by resistance values, lower resistance for parallel and higher resistance for anti-parallel states. The resistances in state 0 or 1 are about 5 KΩ or 10 KΩ, respectively, and the program currents are about +/−100-200 μA. One example of programming an MRAM cell is described in T. Kawahara, “2 Mb Spin-Transfer Torque RAM with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read,” International Solid-State Circuit Conference, 2007, pp. 480-481.